The present invention relates to metal oxide semiconductor field effect transistors (MOSFETs) and, more particularly, to body-tied-to-source MOSFETs and methods of fabricating the same.
As electronic appliances using semiconductor devices decrease in size and weight, it is desirable that the semiconductor devices have higher density per unit area, lower threshold voltage Vt, faster operating speed, and lower power consumption. Semiconductor devices widely employ transistors, such as metal oxide semiconductor (MOS) transistors, as switching devices. In response to the desire for high density, methods of stacking a plurality of transistors on a limited area of a semiconductor substrate are now under investigation. A typical method of stacking the transistors includes forming a lower transistor on the semiconductor substrate, forming an insulating layer covering the lower transistor, and forming a thin film transistor (TFT) on the insulating layer. However, stacking transistors can present several difficulties.
A technique for forming a transistor on a silicon-on-insulator (SOI) can provide advantages of low junction capacitance and good isolation characteristics, so it is widely applied in forming semiconductor devices with high-speed operation and low power consumption. In addition, an SOI MOS transistor can provide a low soft error rate and good latch-up characteristics.
Typical TFT and SOI MOS transistors have an insulating layer disposed on a semiconductor substrate, and a semiconductor layer, which is referred to as a body, disposed on the insulating layer. FIG. 1 is a cross-sectional view schematically illustrating a conventional SOI MOS transistor. The SOI MOS transistor includes an insulating layer 2 disposed on a semiconductor substrate 1. A body 3, a source 4, and a drain 5 are disposed on the insulating layer 2. A gate electrode 7 is disposed on the body 3, and a gate insulating layer 6 is interposed between the body 3 and the gate electrode 7.
The body 3 is in a floating state, that is, the body 3 of the SOI MOS transistor is isolated from the semiconductor substrate 1 due to the insulating layer 2, so that a voltage of the body 3 may change in response to a voltage applied to the source 4, the drain 5 and the gate electrode 7. Voltage variation of the body 3, referred to as a floating body effect, can impede proper operation of the SOI MOS transistor. Associated harmful effects include a kink effect and a parasitic bipolar effect.
When the body 3 is partially depleted and a high voltage is applied to the drain 5, an electric field generated in the MOS transistor can cause impact ionization near the drain 5. As a result, when the MOS transistor is an NMOS transistor, holes generated by the impact ionization may be injected into the body 3, so that the body 3 is charged with positive electric charges. These positive electric charges accumulated in the body 3 can increase the potential of the body 3, which can cause a threshold voltage of the MOS transistor to be decreased. The decrease of the threshold voltage allows the drain current to increase, so that a kink phenomenon may occur in output characteristics of the MOS transistor.
The charged body 3 may also turn on a lateral bipolar transistor structure, i.e., an n-p-n structure including the source 4, the body 3, and the drain 5. When the body 3 of the MOS transistor becomes biased with a positive voltage, a forward bias is applied to a junction between the source 4 and the body 3 corresponding to a junction between an emitter and a base of the lateral n-p-n structure, so that electrons may be injected from the source 4 to the body 3. The electrons injected into the body 3 reach a drain depletion region to be added to a drain current. As a result, the drain current may be mainly controlled by a parasitic bipolar transistor, rather than a channel current flowing under the control of the gate electrode 7. Such an effect is referred to as a parasitic bipolar effect. The parasitic bipolar operation of the MOS transistor can cause undesirable leakage current.
Some techniques have been proposed in order to reduce harmful effects associated with the floating body effect. For example, some research has been conducted on methods of directly applying an external voltage to the body 3. However, these methods may require an additional interconnection. The additional interconnection can limit the degree of integration of a semiconductor device.
Research has also been conducted on methods of connecting the body 3 to the gate electrode 7. However, these methods may not avoid the problem of dynamic leakage current between the source and the drain when the gate voltage is high and the source and drain voltages are low. In addition, potentials between the body 3, the source 4, and the drain 5 typically change according to on and off states of the MOS transistor.
Methods of connecting the body 3 to the source 4 have also been proposed. These methods of connecting the body 3 to the source 4 may be effectively used when sources are fixed to Vcc or Vss, as in a driver transistor and a load transistor of a static random access memory (SRAM) cell.
Methods of connecting a body to a source in an SOI MOS transistor are disclosed in U.S. Pat. No. 6,111,293 entitled “Silicon-on-insulator MOS structure” to Liao. In this patent, a SOI MOS structure includes a double implanted source region.
A body region, a source region, a drain region, and an insulated gate electrode are formed on an SOI semiconductor substrate. A nitride layer is formed on the gate electrode. First conductivity type impurity ions are implanted into the source region and the drain region using the nitride layer and the gate electrode as ion implantation masks. An ion implantation mask is then formed to cover the drain region and expose the source region. Second conductivity type impurity ions are implanted into the source region using the ion implantation mask. As a result, the source region is divided into an upper impurity region and a lower impurity region. A metal contact plug is then formed to penetrate the upper impurity region and contact with the lower impurity region. Consequently, a structure is formed such that the upper impurity region and the lower impurity region are electrically connected to the metal contact plug. In addition, the metal contact plug is electrically connected to the body region through the lower impurity region. However, when impurity ions are implanted into the source region over two times, an interface between the upper impurity region and the lower impurity region may not be explicit and a junction characteristic of the upper impurity region may be degraded.
In light of the foregoing, there is an ongoing need for techniques for enhancing the characteristics of a MOS transistor having a body region disposed on an insulating layer.